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Using a Serial EEPROM | Cypress Semiconductor

Using a Serial EEPROM

Last Updated:

October 11, 2011

Upon power-up or reset, the PCI-DP will initialize the PCI configuration space/operation registers to the values set in the external serial EEPROM (if present and enabled). In order for the serial EEPROM to configure the PCI-DP at power-up, it must be located at device address 0. After writing correct values in the memory space allotted for the configuration data, a valid CY7C09449PV signature of 0x4837 is located at address 0x43 - 0x42. Otherwise, the PCI-DP will not recognize the memory contents as valid configuration data.

If the configuration space is being corrupted, then it is likely happening during programming of the EEPROM (in this case you can try reading back the memory map from EEPROM to ensure valid data before power-down). The Vendor ID field is read-only from the PCI side.

If there are still problems, power-up the card in a known state, by disabling the EEPROM (change the PCI-DP signature bytes) so that the default values are loaded from the silicon. Similarly, the PCI-DP will work with an erased EEPROM. If no values are in the EEPROM, the default values stored inside the PCI-DP will be used. In many cases that means the local bus will not work, but you will be able to access the device through the PCI side. You would have to write data into your operations registers from the PCI side to enable proper functionality of the local bus interface.

The PCI-DP supports the I2C serial EEPROM. The device type identifier should begin with 1010 and it should be comparable in operation to the Xicor X24C02 or Microchip 24LC02 EEPROMs. Using a larger 1K x 8 EEPROM (i.e. Microchip 24LC64) will cause some problems. In the smaller device, addressing is only a single 8-bit address rather than the "high byte" and "low byte" of the larger 1K x 8 EEPROM. As such, if you compare how reading and writing is done in the two devices, you will see that in the smaller EEPROM, there is a start bit, then a single control byte, a single address byte, followed by a single data byte, and finally a stop bit. In the larger EEPROM, there is a start bit, a control byte, then two address bytes, followed by the data byte and stop bit. So the problem is that a larger EEPROM is looking for a second address byte.