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Synchronous SRAM (Sync SRAMs) | Cypress Semiconductor

Synchronous SRAM (Sync SRAMs)

Synchronous Static Random-Access Memory (Sync SRAMs)

Sync SRAMs with on-chip Error correcting code

 

Sync SRAMs is a type of volatile random-access memory (RAM) that uses flip-flop based latching circuitry to store each bit. The data bits are retained in memory as long as power is supplied. Unlike Async SRAM, Sync SRAMs has a clocked interface for control, address and data. Infineon provides the Industry’s broadest portfolio of Synchronous SRAMs from 2M to 144M.

Infineon’s Sync SRAMs are RoHS compliant, QML certified for Defense products and available in industry standard TSOP. BGA, SOP packages

Parallel (x8, x16, x32, x72)

  • 2M
  • 4M
  • 9M
  • 18M
  • 36M
  • 72M
  • 144M
  • Infineon’s Synchronous SRAM is used in leading Computed Tomography (CT), Positron Emission Tomography (PET), and Ultrasound medical imaging systems as buffers to enable real-time high definition image processing
  • Sync SRAMs are used in POS/ Network printers
  • Infineon’s QDR SRAM is available to the space community with RadStop technology radiation hardening through proprietary process enhancement and circuit design.
  • Infineon’s QDR-IV SRAM with RTR of 2132 MT/s are used in High speed networking devices
  • Infineon’s Sync SRAM are used in Industrial PLC’s for its Lowest Soft error rate of <0.1 FIT/Mbit

Wide portfolio

Wide portfolio

Over 2,300 different SRAM products

Highest RTR

Highest RTR

Industry leading Random Transaction Rate of 2132 MT/s

High reliability

High reliability

On-Chip ECC to provide lowest Soft error rate <0.1FIT/Mbit

Long term support

Long term support

Legacy support for up to 20 years

 

What is Synchronous SRAM (Sync SRAM)?

SRAMs come in two different flavors: Synchronous and Asynchronous. Synchronous SRAMs are devices that are synchronized with an external signal called a clock. The device will read and write information into the memory only on particular states of the clock. An asynchronous SRAM, on the other hand, does not depend on the state of a clock. It will begin to read or write information into the memory as soon as it receives the instruction to do so. Click here to know more about Infineon’s Asynchronous SRAM products.

Infineon’s Sync SRAM Memory Family

Infineon offers a comprehensive portfolio of Sync SRAMs including Standard Sync SRAM, NoBL™ SRAM, DDR/QDR SRAM.

Standard Sync SRAMs were created especially for cache applications. These devices incorporate an internal 2-bit burst counter that supports a cache line size of four. These are available in densities ranging from 2 Mbit to 72 Mbit.

No Bus Latency (NoBL™) Sync SRAMs: Commonly known as Zero bus Turn-around (ZBT) SRAMs, they require no idle cycles when the bus is turned around, that is, when it transitions from Read to Write, or Write to Read. Two versions of NoBL SRAM exist: Flow-through and Pipelined. NoBL Flow-through SRAMs always have a one clock cycle delay from address to data in the system. Pipelined NoBL SRAM requires an additional pipelined register in the device output. These are available in densities ranging from 2 Mbit to 144 Mbit.

DDR-II/II+/II+ Xtreme Sync SRAMs: DDR stands for Dual Data Rate. DDR-II SRAMs have common Read and Write ports. These are similar to the legacy Synchronous Burst SRAM products but with double data rate I/Os. They are suitable for read intensive functions such as packet look up and packet classification in networking/ communication applications.

QDR-II/II+/II+ Xtreme Sync SRAMs: QDR stands for Quad Data Rate. QDR-II SRAMs were developed to address network applications that require the low latency and full cycle utilization of NoBL SRAMs but also require a significantly higher operating frequency. QDR-II SRAMs have separate Read and Write buses. QDR SRAM memories are available in densities ranging from 18 Mbit to 144 Mbit

QDR-IV Sync SRAMs: The QDR-IV SRAMs are high-performance memory devices optimized to maximize the number of random transactions per second by the use of two independent bidirectional data ports. QDR SRAMs are used in networking applications where reads and writes are balanced such as packet buffer, statistics counters, flow state, and scheduling. They are available in 72 Mbit and 144 Mbit densities with the Random Transaction Rate (RTR) required for 100-400 Gigabit line cards in switches and routers

This application note will help you choose the right Synchronous SRAM for your application.

What is Random Transaction Rate (RTR)?

Random Transaction Rate (RTR) is the number of fully random read or write transactions a memory can perform every second. It is measured in MT/s, or mega transactions per second. RTR is a critical metric in high-performance computing, general-purpose servers, and image-processing applications., where memory access is unpredictable.

The QDR consortium defined QDR™ (Quadruple Data Rate) SRAM products are geared primarily to the networking and communication market. QDR SRAMs allows access to any two memory locations on every clock cycle, and performance never depends on which memory location was accessed in the previous clock cycle. Hence, with QDR SRAM, RTR is guaranteed.

QDR-IV SRAMs are capable of operating in burst-of-two or banked burst-of-two modes, which deliver the fastest clock speeds and highest RTR of all QDR SRAMs and also higher than competing RLDRAMs and DDR3 DRAMs.

Cypress' QDR-IV SRAM provides RTR up to 2132 MT/s.

Infineon’s QDR-IV SRAM provides Random Transaction Rate(RTR) up to 2132 MT/s

About Infineon RAM Memory Solutions

With over 3 decades of leadership in the memory business, Infineon offers a broad portfolio of volatile and non-volatile memories. Our volatile memory offerings include Synchronous and Asynchronous SRAMs for the lower densities and HyperRAMs for the higher densities. Our non-volatile portfolio includes F-RAM and nvSRAM products.

Infineon Products

Synchronous static random-access memory (Sync SRAM)

Infineon’s high-speed synchronous SRAMs include standard synchronous pipelined, No Bus Latency™ (NoBL™), Quad Data Rate™ (QDR™), and Double Data Rate (DDR) SRAMs. Learn More.

Standard Sync SRAMs
With On-chip ECC
Density:
2Mb - 72Mb
Core Voltage:
2.5V, 3.3V
Data width:
x18, x32, x36, x72
Random Transaction Rate:
250 MT/s
Maximum bandwidth:
18 Gbps
On-Chip ECC:
Yes
Temperature Grade:

Industrial

Commercial

NoBL Sync SRAMs
No Bus Latency for High speed applications
Density:
4Mb - 72Mb
Core Voltage:
2.5V, 3.3V
Data width:
x18, x32, x72
Random Transaction Rate:
250 MT/s
Maximum bandwidth:
18 Gbps
On-Chip ECC:
Yes
Temperature Grade:

Industrial

Commercial

DDR Sync SRAMs
With Max RTR of 666MT/s
Density:
18Mb - 144Mb
Core Voltage:
1.8V
Data width:
x8, x9, x18, x36
Random Transaction Rate:
666 MT/s
Maximum bandwidth:
47.9 Gbps
On-Chip ECC:
No
Temperature Grade:

Industrial

Commercial

QDR-II+ SRAMs
With On-die termination
Density:
36Mb - 72Mb
Core Voltage:
1.8V
Data width:
x18, x32, x36, x72
Random Transaction Rate:
666 MT/s
Maximum bandwidth:
79.2 Gbps
On-die termination:
Yes
Temperature Grade:

Industrial

Commercial

QDR-II+ Xtreme
With On-die termination
Density:
36Mb - 72Mb
Core Voltage:
1.8V
Data width:
x18, x36
Random Transaction Rate:
900 MT/s
Maximum bandwidth:
91.1 Gbps
On-die termination:
Yes
Temperature Grade:

Industrial

Commercial

QDR-IV
With On-die termination & On-chip ECC
Density:
72Mb - 144Mb
Core Voltage:
1.3V
Data width:
x18, x36
Random Transaction Rate:
2132 MT/s
Maximum bandwidth:
153.3 Gbps
On-die termination:
Yes
Temperature Grade:

Industrial

Commercial

Document Type Standard Sync NoBL QDR-II QDR-II+ QDR-II+ Xtreme QDR-IV
Product Roadmaps 1 1 1 1 1 1
Advanced Product Change Notice (APCN)            
Application Notes 2 3 5 7   1
Datasheets 14 13 9 25 8 4
Errata   1        
Models 36 26 94 77 3 18
Other Resources     2 2   1
Product Brochures            
Product Change Notice (PCN)            
Product Information Notice (PIN)            
Product Overviews       1   2
Qualification Reports 3 4 3 3   1
Technical Articles           1
White Papers           1
Knowledge Base Articles 148
High-Speed Networking
    Military and Aerospace
      High Performance Computing
        Imaging and Video