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PSoC Designer | Cypress Semiconductor

PSoC Designer

PSoC Designer is a revolutionary Integrated Design Environment (IDE) that enables you to customize PSoC 1 devices to meet your application requirements. PSoC Designer accelerates system bring-up and time-to-market by providing a library of pre-characterized analog and digital peripherals, called User Modules, in a simple, drag-and-drop design environment. This helps in customizing your design by leveraging the dynamically generated API libraries of code. PSoC Designer also enables you to debug and test your designs with the integrated debug environment, including in-circuit emulation and standard debug features. PSoC Designer features the following:

  • An Application Editor Graphical User Interface (GUI) for device and User Module configuration and dynamic reconfiguration
  • 150+ User Modules for design customization
  • Integrated Source Code Editor (C and Assembly)
  • Free C-compiler with no size restrictions or time limits
  • Built-in Debugger
  • Integrated Circuit Emulation (ICE)
  • Built-in support for Communication Interfaces:
    • Full-Speed USB 2.0
    • Hardware and software I2C slaves and masters
    • Up to 4 full-duplex UARTs, SPI master and slave, and Wireless

PSoC Designer Frequently Asked Questions (FAQ)

A frequently asked questions (FAQ) guide is available for PSoC Designer. This includes answers to common questions about PSoC Designer and the PSoC 1 device family. This can be accessed on the PSoC Designer FAQ webpage.

Use PSoC Designer to unlock the power of PSoC

PSoC Designer 5.4 SP1

  • New devices supported - CY8C20075 and CY7C64346
  • BootLdrI2C User Module support for CY8C20055 device family
  • Improved auto-complete code editor function
  • Upgraded CapSense FMEA and Background Scanning features in CSD2x, SmartSense2X, and SmartSense2X_EMC User Modules
  • Updated compiler optimization for CapSense User Modules

For access to past releases of PSoC Designer please navigate to the PSoC Designer Archives page. For users who wish to develop using the obsolete System Level Editor please navigate to the archived PSoC Designer 5.0 SP6 web page.

This is the tool that started it all; the original IDE for PSoC that first combined the configuration of devices with the development of software. Now in its fifth revision (PSoC Designer 5.0 was released in Summer of 2008), this is the tool that introduced graphical chip setup, parameterized user modules, any-function-to-any-pin routing, and automatic API generation.

Choose from a library of configurable analog and digital modulesConnect User Modules and PinsConfigure User Modules


PSoC Designer offers a wide array of configurable, pre-characterized, analog and digital building blocks to implement a range of functions and peripherals that are typically separate parts which cannot be configured (or reconfigured) on the fly.  The configurability of the User Modules accommodates application-specific tailoring and last minute changes.

Examples of User Modules provided with PSoC Designer include

  • ADCs and DACs
  • Amplifiers, Comparators, and Analog Multiplexers
  • Filters
  • Counters, Timers and PWMs
  • Star Network Protocol (SNP) stack that implements hub or node functionality to support a wireless star network
  • Temperature measurement
  • Digital communications blocks like I2C, UART, SPI.
  • Special function blocks like LED/LCD Drivers. 
  • Capacitive touch solutions (touch screens, buttons, sliders, proximity sensing, etc.)
  • Auto-Tuning Capacitive Sensing User Module. Requires no manual tuning whatsoever. Automatic, in-system determination of all CapSense parameters.

Every User Module has a comprehensive data sheet, available from the software or on the web.

Accelerate Your Device Configuration

Global Resource settings in PSoC Designer enable you to configure system level registers through an easy to use graphical user interface. This unique approach enables rapid system level configuration without manually writing system configuration registers. No more arcane boot code to hack nor processor architectures to learn!

This application note discusses all the resources available and their corresponding settings. It also carefully explains which registers are affected by your selections and recommends some best practices for first time success and long-term maintainability.