FIFO / Dual-port SRAMs

Quad Data Rate (QDR) SRAM

The QDR consortium defined QDR (Quadruple Data Rate) SRAM products are geared primarily to the networking and communication market. The QDR SRAMs are similar to NoBL SRAMs but with architectural enhancements such as double data rate I/Os, and dedicated read write ports. The QDR SRAMs are used in networking applications where reads and writes are balanced such as packet buffer, statistics counters, flow state, and scheduling. The QDR SRAMs have a maximum clock speed of 167 MHz with a read latency of 1 cycle and are available in an industry standard 165 Ball BGA.

DDR SRAM

The QDR consortium defined DDR CIO SRAMs are similar to the legacy Synchronous Burst SRAM products but with double data rate I/Os. Like the Synchronous Burst SRAMs they are used for read intensive functions such as packet look up and packet classification in networking/communication applications. The DDR SRAMs have a maximum clock speed of 167 MHz with a read latency of 1 cycle and are available in an industry standard 165 Ball BGA

DDR-II CIO SRAM

The DDRII SRAMs are similar to DDR SRAMs in their operation but with some performance improvements. The DDRII SRAMs include source synchronous free running echo clocks (CQ, /CQ) that enable customers to easily capture data. The DDRII SRAMs also support 1.5V HSTL interface. The applications are the same as that of DDR SRAMs. The DDRII SRAMs have a maximum speed of 333 MHz with a read latency of 1.5 cycles, with burst lengths of 2 and 4, and are available in an industry standard 165 Ball BGA.

DDR-II SIO SRAM

The DDRII SIO SRAMs are similar to DDRII CIO SRAMs but they include two separate ports: the read port and the write port to access the memory array. The read port has data outputs to support read operation and the write port has data inputs to support write operation. The DDR II SIO SRAM completely eliminates the need to "turnaround" the data bus required with common I/O devices.

DDR-II + CIO SRAM

The DDRII+ SRAMS are similar to DDRII+ SRAMs in their operation but with additional performance improvements. The redundant data input clocks (C & /C) are not present in the DDRII+ suite of products. Instead DDRII SRAMs include a hand shake signal (QVLD) that indicates when the Data will become valid thereby simplifying data capture. The customers also have the choice of QDRII products with programmable ODT (On Die Termination). The ODT feature turns on during a write cycle and turns off during a read cycle to save power. The DDRII+ SRAMs have a maximum speed of 550 MHz with read latencies of either 2 cycles or 2.5 cycles, with a burst length of 2 and are available in an industry standard 165 Ball BGA.

DDR-II + SIO SRAM

Cypress’ high-speed synchronous SRAMs include standard synchronous pipelined, No Bus Latency™ (NoBL™), Quad Data Rate™ (QDR™), and Double Data Rate (DDR) SRAMs, and are typically used in networking applications. Cypress Synchronous SRAMs are the ideal solution for networking applications such as Look-up tables, Link Lists, Que Management, Policing and Packet buffers. The Cypress synchronous SRAM portfolio is comprised of hundreds of memories in a variety of speeds, bus widths, densities and packages. Using industry standard pin outs, Cypress Synchronous SRAM products are easily integrated into new and existing designs.

Dual port SRAM

Cypress is a market leader in multi-port memory solutions, offering highest performance interconnects solutions in the industry. Cypress offers a wide Product portfolio of more than 300 types of Asynchronous and Synchronous Dual Ports, Quad Ports and FullFlex Dual Ports.

MoBL Dual port SRAM

Cypress offers a variety of high performance and low power Inter-Processor Communication (IPC) solutions. These interconnects allow IPC between multiple processors in various applications. Our MoBL® family of Dual-Ports is specially optimized for consumer and handheld devices.

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