DDR | Cypress Semiconductor


The QDR consortium defined DDR CIO SRAMs are similar to the legacy Synchronous Burst SRAM products but with double data rate I/Os. Like the Synchronous Burst SRAMs they are used for read intensive functions such as packet look up and packet classification in networking/communication applications. The DDR SRAMs have a maximum clock speed of 167MHz with a read latency of 1 cycle and are available in an industry standard 165 Ball BGA

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  1. Download the DDR-II SRAM Design Guide
  2. Download the DDR-II Datasheets