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Cypresss HOTLink II(TM) PHYs Meet CPRI Radio Control Link Specification | Cypress Semiconductor

Cypresss HOTLink II(TM) PHYs Meet CPRI Radio Control Link Specification

Last Updated: November 03, 2004

Backplane PHY Transceivers Address Key Internal Interface of Radio Basestations Between the Radio Equipment Control and the Radio Equipment

Cypress PR

SAN JOSE, Calif., November 3, 2004 - Cypress Semiconductor Corp. (NYSE: CY) today announced that its industry-leading HOTLink II(TM) physical layer (PHY) family meets the Common Public Radio Interface (CPRI) specification version 1.2.  CPRI focuses on a 3G radio basestation design that divides the radio basestation into a radio and a control part, by specifying one new interface - the only and unique radio driven interconnect point within basestations. This will enable each part of the basestation to better benefit from the technology evolution in its respective area.

The CPRI specification is openly available for the benefit of the wireless industry. Key benefits for Network Operators are the availability of wider radio basestation portfolios providing adaptability to all deployment scenarios with a shorter time to market. The CPRI specification enables basestation manufacturers and component vendors to focus their research and development efforts on their core competencies and also allows for new architectures not limited by module dimensions or a pre-defined function split.

"The CPRI spec defines a single, standardized interface between the digital components of a basestation and the RF segment, thus creating cost-reduction and faster time to market opportunities at one of the most critical serial links of a system," said Erin Kettwig, product manager for Cypress's Data Communications Division. "By using Cypress's HOTLink II family of PHYs, system vendors are guaranteed a simplified integration with hardware developed independently on either side of the interface."

Cypress is a long-time supplier of backplane PHY transceivers that enable the transport of data over high-speed serial links (optical fiber, balanced and unbalanced copper transmission lines, and board traces). The HOTLink II family of PHY devices supports serial data rates of 614.4 Mbps and 1228.8 Mbps on any channel within a single chip. The chips also include a multi-byte framer for more robust framing in CDMA, W-CDMA and GSM/EDGE applications, and support selectable Comma (K28.5) character framing options between both message groups and master frames.  Cypress's HOTLink II devices all feature low jitter, 8B/10B ENDEC capabilities, and are available in single-, dual-, quad-, and independent-channel configurations. 

Pricing and Availability:
The HOTLink II(TM) family of CPRI-compliant physical layers is available now, priced as listed in the table below:

Part Number

Channel Configuration

1Ku Price



1 Transceiver Channel




2 Transceiver Channels




4 Transceiver Channels




4 Independent Transceiver Channels



About Cypress
Cypress Semiconductor Corporation (NYSE: CY) is Connecting From Last Mile to First Mile(TM) with high-performance solutions for personal, network access, enterprise, metro switch and core communications-system applications. Cypress Connects(TM) using wireless, wireline, digital and optical transmission standards, including USB, Fibre Channel, SONET/SDH, Gigabit Ethernet and DWDM. Leveraging its process and system-level expertise, Cypress makes industry-leading physical layer devices, framers and network search engines, along with a broad portfolio of high-bandwidth memories, timing technology solutions and reconfigurable mixed-signal arrays. More information about Cypress is accessible online at

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Cypress and the Cypress logo are registered trademarks of Cypress Semiconductor Corporation. HOTLinkII, "Connecting From Last Mile to First Mile" and "Cypress Connects" are trademarks of Cypress. All other trademarks are the property of their respective owners.

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