DFB assembler and (Significantly) Improved Simulator component | Cypress Semiconductor
DFB assembler and (Significantly) Improved Simulator component
This was a joint component improvement effort by myself and Dan Sweet (DRSW, a fellow apps engineer).
We were doing some development with the DFB and came to realize what a frustrating experience it was to learn and program the DFB. The documentation needs a significant overhaul, but in the meantime, a much better simulator was an absolute must. Dan and I spent weeks pouring over documents, memos and other information and learning everything we could about the DFB. The fruits of our labor allowed us to climb into the simulator and provide *significantly* more information to the intrepid DFB programmer when using the simulator. The new simulator now shows:
- A1 / B1 mux ouptut and mux arm selection
- ACU ram address, ACU A / B operation, A / B RAM write and read addresses and write enable signal
- A2 / B2 mux output and mux arm selection
- Mac A / B inputs, operation and output (upper 24 bits of accumulator)
- A3 / B3 mux outputs and mux arm selection
- ALU A / B inputs, operation and output
- shifter operation and output
- reads from holding registers, writes to output registers and A / B RAM
The simulation also includes a significantly expanded simulation properties window that shows:
- ACU A / B internal registers (LREG, MREG, FREG, REG, mod enable)
- current jump conditions (in1, in2, acuaeq, acubeq, dpeq, dpsign, dpthresh, global jump enable, semaphore jump enable)
- ALU internal variables (rounding flag, saturation enable, saturation flag, squelch count, squelch value)
- global input signals (writeable)
- semaphore values (readable / writeable)
- ACU A / B RAM contents
- Datapath A / B RAM contents
- Internal execuation values (finite state machine index, CSTORE RAM A / B selection and index) [these values are not needed by the DFB programmer, they are left in for advanced users and assembler debugging]
The attached zip archive includes the component in a library, as well as an archive of the component exported to a .cycomp archive using the component export feature. The archive also includes some memos that talk about code blocks and instruction pipelining, which helps a lot when trying to write code for the heavily pipelined DFB.
An important note, because of the pipelining, an opcode will not necessarily execute immediately. It may occur 1, 2 or 3 instructions later. This is what makes the simulator so valuable. you can observe when the opcodes execute and quickly determine if your data is where it needs to be when the opcode is ready.