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Timing Uncertainty in High Performance Clock Distribution | Cypress Semiconductor

Timing Uncertainty in High Performance Clock Distribution

Last Updated: 
May 28, 2020
Version: 
*B

Several factors contribute to the timing uncertainty when using fanout buffers to distribute a clock to synchronize various devices within a system. For non-PLL clock fanout buffers, output skew, propagation delay, and edge rates play a critical role in determining system timing margin. This White Paper briefly discusses these parameters and their effect on system performance.