User Module Datasheet: Delta Sigma ADC Datasheet DelSig V 1.50 (CY8C29xxx, CYC8C24x94, CY7C64215, CY8CLED04/16, CY8CLED0xD, CY8CLED0xG, CY8CTST120, CY8CTMG120, CY8CTMA120, CY8C28x45, CY8CPLC20, CY8CLED16P01, CY8C28x43, CY8C28x52)

Features and Overview

• 6-bit resolution with 32X oversampling to 14-bit resolution with 256X oversampling
• Data in unsigned or signed 2’s complement formats
• Maximum sample rates of 65,500 sps at 6 bit resolution, 7812 sps at 14-bit resolution
• Sinc² filter fully implemented in hardware reduces CPU overhead and anti-alias requirements
• 1st-Order or 2nd-Order modulator, user selectable
• Input range defined by internal and external reference options
• Optional synchronized PWM Output

The DelSig is an integrating converter, requiring from 32 to 256 integration cycles to generate a single output sample. Changing multiplexed inputs, invalidates the first two samples following the change.