User Module Datasheet: 14-BIT INCREMENTAL ADC DATASHEET, ADCINC14 V1.4 (CY8C29/27/24/22XXX, CY8C23X33, CY8CLED04/08/16, CY8C28X45, CY8C28X43, CY8C28X52) | Cypress Semiconductor
User Module Datasheet: 14-BIT INCREMENTAL ADC DATASHEET, ADCINC14 V1.4 (CY8C29/27/24/22XXX, CY8C23X33, CY8CLED04/08/16, CY8C28X45, CY8C28X43, CY8C28X52)
Features and Overview
14-bit resolution, 2’s complement
Sample rate from 2 to 120 sps
Input range from Vss to Vdd
Integrating converter provides good normal mode rejection
Internal or external clock
The ADCINC14 is an integrating ADC with 14 bits of resolution. It can be configured to remove unwanted high frequencies by optimizing the integrate time. Input voltage ranges, including rail-to-rail, may be measured by configuring the proper reference voltage and analog ground. The result format is selectable between signed or unsigned, based on an input voltage between -Vref and Vref centered at AGND.
Sample rates from 2 to over 120 sps are achievable, depending on the selection of the DataClock and CalcTime parameters. The programming interface allows you to specify the number of sequential samples to be taken or to select continuous sampling. The CPU load varies with the input level. For example, when Vin = Vref, there are 9832 CPU cycles (maximum 13 bit). When Vin = AGND, there are 5076 CPU cycles. When Vin = -Vref, there are 360 CPU cycles.