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S6E1A1 Reset Factor | Cypress Semiconductor

S6E1A1 Reset Factor

Last Updated: 
Jun 17, 2016

This software example demonstrates the usage of the Reset Status register.
It is read out and the reset causes are display to the user via UART.
If the MCU reset was caused by clock failure or anomalously clock frequency the clock source is not switched to Main/Sub clock/PLL into the system_s6e2cc.c file while startup and remains on high-speed CR clock.
Reset by hardware or software watchdog and software reset can be triggered via UART Terminal.
KEIL: Please check "Project — Options — Target — NoInit" for RAM!

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