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Cache + MPU SW example project for MB9DF126 | Cypress Semiconductor

Cache + MPU SW example project for MB9DF126

Last Updated: 
Jun 21, 2016

Cache + MPU SW example project for MB9DF126, demonstrating effect of data manipulation by CPU and other bus masters while D-cache is enabled. A MPU region is configured as non-cacheable to prevent the effect of inconsistent data.

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