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S80KS5123, 1.8 V, 512-Mbit, Octal xSPI Interface HyperRAM (Self-Refresh DRAM) | Cypress Semiconductor

S80KS5123, 1.8 V, 512-Mbit, Octal xSPI Interface HyperRAM (Self-Refresh DRAM)

Last Updated: 
Aug 10, 2021
Version: 
*B
The Cypress 512-Mb HyperRAM device is a high-speed CMOS, self-refresh DRAM, with xSPI (Octal) interface. The DRAM array uses dynamic cells that require periodic refresh. Refresh control logic within the device manages the refresh operations on the DRAM array when the memory is not being actively read or written by the xSPI interface master (host). Since the host is not required to manage any refresh operations, the DRAM array appears to the host as though the memory uses static cells that retain data without refresh. Hence, the memory is more accurately described as Pseudo Static RAM (PSRAM). Since the DRAM cells cannot be refreshed during a read or write transaction, there is a requirement that the host limit read or write burst transfers lengths to allow internal logic refresh operations when they are needed. The host must confine the duration of transactions and allow additional initial access latency, at the beginning of a new transaction, if the memory indicates a refresh operation is needed. The dual-die, 512-Mb HyperRAM chip supports data transactions with additional (2X) latency only.

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