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CYWT1542AV18/CYWT1544AV18, 72-Mbit QDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) | Cypress Semiconductor

CYWT1542AV18/CYWT1544AV18, 72-Mbit QDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency)

Last Updated: 
Jun 30, 2020
Version: 
*A

The CYWT1542AV18, and CYWT1544AV18 are 1.8 V synchronous pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ SRAMs consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. QDR II+ architecture has separate data inputs and data outputs to completely eliminate the need to “turn around” the data bus that exists with common I/O devices. Each port is accessed through a common address bus. Addresses for read and write addresses are latched on alternate rising edges of the input (K) clock. Accesses to the QDR II+ read and write ports are completely independent of one another. To maximize data throughput, both read and write ports are equipped with DDR interfaces. Each address location is associated with two 18-bit words (CYWT1542AV18), or 36-bit words (CYWT1544AV18) that burst sequentially into or out of the device. Because data is transferred into and out of the device on every rising edge of both input clocks (K and K), memory bandwidth is maximized while simplifying system design by eliminating bus “turn-arounds”. Depth expansion is accomplished with port selects, which enables each port to operate independently. All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the K or K input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry.