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CYF0018V, CYF0036V, CYF0072V: 18/36/72-Mbit Programmable FIFOs | Cypress Semiconductor

CYF0018V, CYF0036V, CYF0072V: 18/36/72-Mbit Programmable FIFOs

Last Updated: 
Nov 28, 2017

18/36/72-Mbit Programmable FIFOs


  • Memory organization
    • Industry's largest first in first out (FIFO) memory densities: 18 Mbit, 36 Mbit, and 72 Mbit
    • Selectable memory organization: x9, x12, x16, x18, x20, x24, x32, x36
  • Up to 133-MHz clock operation
  • Unidirectional operation
  • Independent read and write ports
    • Supports simultaneous read and write operations
    • Reads and writes operate on independent clocks, upto a maximum ratio of two, enabling data buffering across clock domains.
    • Supports multiple I/O voltage standard: low voltage complementary metal oxide semiconductor (LVCMOS) 3.3 V and 1.8 V voltage standards.
  • For more, see pdf.

Functional Description

The Cypress programmable FIFO family offers the industry’s highest-density programmable FIFO memory device. It has independent read and write ports, which can be clocked up to 133 MHz. User can configure input and output bus sizes. The maximum bus size of 36 bits enables a maximum data throughput of 4.8 Gbps.

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