CY7C2268XV18/CY7C2270XV18, 36-MBIT DDR II+ XTREME SRAM TWO-WORD BURST ARCHITECTURE (2.5 CYCLE READ LATENCY) WITH ODT | Cypress Semiconductor
CY7C2268XV18/CY7C2270XV18, 36-MBIT DDR II+ XTREME SRAM TWO-WORD BURST ARCHITECTURE (2.5 CYCLE READ LATENCY) WITH ODT
36-Mbit DDR II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT
- 36-Mbit density (2 M × 18, 1 M × 36)
- 633 MHz clock for high bandwidth
- 2-word burst for reducing address bus frequency
- Double data rate (DDR) interfaces (data transferred at 1266 MHz) at 633 MHz
- Available in 2.5 clock cycle latency
- Two input clocks (K and K) for precise DDR timing
- Echo Clocks (CQ and CQ) simplify data capture in high speed systems
- Data valid pin (QVLD) to indicate valid data on the output
- On-die termination (ODT) feature
- Synchronous internally self-timed writes
- For more, see pdf
The CY7C2268XV18, and CY7C2270XV18 are 1.8 V Synchronous Pipelined SRAMs equipped with DDR II+ architecture. The DDR II+ consists of an SRAM core with advanced synchronous peripheral circuitry. Addresses for read and write are latched on alternate rising edges of the input (K) clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of K and K. Each address location is associated with two 18-bit words (CY7C2268XV18), or 36-bit words (CY7C2270XV18) that burst sequentially into or out of the device.
Dear valued customer,
Thank you for choosing our products. They come with all the know-how and passion that our engineers have put into it. As you probably already know, Cypress is now Infineon. This is a major step for our company, but also for the good of you.
Reliability and business continuity are of utmost importance for us. Hence, we remain fully committed to honoring existing customer and distributor relationships. This includes offering the legacy Cypress product portfolio. We thank you very much for your trusting support.
For the full version of this message, please download the PDF version.