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CY7C1623KV18: 144-Mbit DDR-II SIO SRAM Two-Word Burst Architecture | Cypress Semiconductor

CY7C1623KV18: 144-Mbit DDR-II SIO SRAM Two-Word Burst Architecture

Last Updated: 
May 28, 2020

144-Mbit DDR-II SIO SRAM Two-Word Burst Architecture

  • 144-Mbit density (8 M × 18)
  • 333 MHz clock for high bandwidth
  • Two-word burst for reducing address bus frequency
  • Double Data Rate (DDR) interfaces (data transferred at 666 MHz) at 333 MHz
  • Two input clocks (K and K) for precise DDR timing
    • SRAM uses rising edges only
  • Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches
  • Echo clocks (CQ and CQ) simplify data capture in high speed systems
  • Synchronous internally self timed writes
  • For more, see pdf.

Functional Description
The CY7C1623KV18 is 1.8 V Synchronous Pipelined SRAM, equipped with DDR-II SIO (Double Data Rate Separate I/O) architecture. The DDR-II SIO consists of two separate ports: the read port and the write port to access the memory array. The read port has data outputs to support read operations and the write port has data inputs to support write operations. The DDR-II SIO has separate data inputs and data outputs to completely eliminate the need to ‘turnaround’ the data bus required with common I/O devices. Access to each port is accomplished through a common address bus.

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