CY7C1618KV18, CY7C1620KV18: 144-Mbit DDR II SRAM Two-Word Burst Architecture | Cypress Semiconductor
CY7C1618KV18, CY7C1620KV18: 144-Mbit DDR II SRAM Two-Word Burst Architecture
144-Mbit DDR II SRAM Two-Word Burst Architecture
- 144-Mbit density (8 M × 18, 8 M × 36)
- 333 MHz clock for high bandwidth
- 2-word burst for reducing address bus frequency
- Double data rate (DDR) interfaces (data transferred at 666 MHz) at 333 MHz
- Two input clocks (K and K) for precise DDR timing
- Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches
- Echo clocks (CQ and CQ) simplify data capture in high-speed systems
- Synchronous internally self-timed writes
- DDR II operates with 1.5-cycle read latency when DOFF is asserted high
- For more, see pdf
The CY7C1618KV18, and CY7C1620KV18 are 1.8-V synchronous pipelined SRAM equipped with DDR II architecture. The DDR II consists of an SRAM core with advanced synchronous peripheral circuitry and a 1-bit burst counter. Addresses for read and write are latched on alternate rising edges of the input (K) clock.
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