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CY7C1518KV18, CY7C1520KV18: 72-Mbit DDR II SRAM Two-Word Burst Architecture | Cypress Semiconductor

CY7C1518KV18, CY7C1520KV18: 72-Mbit DDR II SRAM Two-Word Burst Architecture

Last Updated: 
Feb 13, 2018

72-Mbit DDR II SRAM Two-Word Burst Architecture


  • 72-Mbit Density (4M x 18, 2M x 36)
  • 333 MHz Clock for High Bandwidth
  • Two-word Burst for reducing Address Bus Frequency
  • Double Data Rate (DDR) Interfaces (data transferred at 666 MHz) at 333 MHz
  • Two Input Clocks (K and K) for precise DDR Timing
    • SRAM uses rising edges only
  • Two Input Clocks for Output Data (C and C) to minimize Clock Skew and Flight Time mismatches
  • Echo Clocks (CQ and CQ) simplify Data Capture in High Speed Systems
  • Synchronous Internally Self-timed Writes
  • DDR II operates with 1.5 Cycle Read Latency when DOFF is asserted HIGH
  • For more, see pdf.

Functional Description

The CY7C1518KV18, and CY7C1520KV18 are 1.8 V synchronous pipelined SRAM equipped with DDR II architecture. The DDR II consists of an SRAM core with advanced synchronous peripheral circuitry and a 1-bit burst counter. Addresses for read and write are latched on alternate rising edges of the input (K) clock.

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