CY7C1471BV33, CY7C1473BV33: 72-Mbit (2 M × 36/4 M × 18) Flow-Through SRAM with NoBL™ Architecture

72-Mbit (2 M × 36/4 M × 18) Flow-Through SRAM with NoBL™ Architecture

Features

• No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles
• Supports up to 133 MHz bus operations with zero wait states
• Data is transferred on every clock
• Pin compatible and functionally equivalent to ZBT™ devices
• Internally self timed output buffer control to eliminate the need to use OE
• Registered inputs for flow through operation
• Byte Write capability
• 3.3V/2.5V I/O supply (VDDQ)
• Fast clock-to-output times
  • 6.5 ns (for 133 MHz device)
• For more, see pdf
   

Functional Description

The CY7C1471BV33 and CY7C1473BV33 are 3.3 V, 2 M × 36/4 M × 18 synchronous flow through burst SRAMs designed specifically to support unlimited true back-to-back read or write operations without the insertion of wait states. The CY7C1471BV33 and CY7C1473BV33 are equipped with the advanced No Bus Latency (NoBL) logic. NoBL™ is required to enable consecutive read or write operations with data being transferred on every clock cycle.