CY7C1471BV33, CY7C1473BV33: 72-Mbit (2 M × 36/4 M × 18) Flow-Through SRAM with NoBL™ Architecture | Cypress Semiconductor
CY7C1471BV33, CY7C1473BV33: 72-Mbit (2 M × 36/4 M × 18) Flow-Through SRAM with NoBL™ Architecture
Last Updated:
Jan 29, 2018
Version:
*K
72-Mbit (2 M × 36/4 M × 18) Flow-Through SRAM with NoBL™ Architecture
Features
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No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles
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Supports up to 133 MHz bus operations with zero wait states
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Data is transferred on every clock
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Pin compatible and functionally equivalent to ZBT™ devices
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Internally self timed output buffer control to eliminate the need to use OE
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Registered inputs for flow through operation
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Byte Write capability
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3.3V/2.5V I/O supply (VDDQ)
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Fast clock-to-output times
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6.5 ns (for 133 MHz device)
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For more, see pdf
Functional Description
The CY7C1471BV33 and CY7C1473BV33 are 3.3 V, 2 M × 36/4 M × 18 synchronous flow through burst SRAMs designed specifically to support unlimited true back-to-back read or write operations without the insertion of wait states. The CY7C1471BV33 and CY7C1473BV33 are equipped with the advanced No Bus Latency (NoBL) logic. NoBL™ is required to enable consecutive read or write operations with data being transferred on every clock cycle.