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CY7C1470V25, CY7C1472V25, CY7C1474V25: 72-Mbit (2 M × 36/4 M × 18/1 M × 72) Pipelined SRAM with NoBL™ Architecture | Cypress Semiconductor

CY7C1470V25, CY7C1472V25, CY7C1474V25: 72-Mbit (2 M × 36/4 M × 18/1 M × 72) Pipelined SRAM with NoBL™ Architecture

Last Updated: 
Jun 09, 2020
Version: 
*V

72-Mbit (2 M × 36/4 M × 18/1 M × 72) Pipelined SRAM with NoBL™ Architecture

Features

  • Pin-compatible and functionally equivalent to ZBT™
  • Supports 200-MHz bus operations with zero wait states
    • Available speed grades are 200 and 167 MHz
  • Internally self-timed output buffer control to eliminate the need to use asynchronous OE
  • Fully registered (inputs and outputs) for pipelined operation
  • Byte write capability
  • Single 2.5 V power supply
  • 2.5 V/1.8 V I/O supply (VDDQ)
  • Fast clock-to-output times
  • For more, see pdf

Functional Description

The CY7C1470V25/CY7C1472V25/CY7C1474V25 are 2.5 V, 2 M × 36/4 M × 18/1 M × 72 synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL™ logic, respectively. They are designed to support unlimited true back-to-back read/write operations with no wait states. The CY7C1470V25/CY7C1472V25/CY7C1474V25 are equipped with the advanced (NoBL) logic required to enable consecutive read/write operations with data being transferred on every clock cycle.

Dear valued customer,

Thank you for choosing our products. They come with all the know-how and passion that our engineers have put into it. As you probably already know, Cypress is now Infineon. This is a major step for our company, but also for the good of you. 

Reliability and business continuity are of utmost importance for us. Hence, we remain fully committed to honoring existing customer and distributor relationships. This includes offering the legacy Cypress product portfolio. We thank you very much for your trusting support.

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