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CY7C1461SV33 36-Mbit (1M × 36) Flow-Through SRAM with NoBL™ Architecture | Cypress Semiconductor

CY7C1461SV33 36-Mbit (1M × 36) Flow-Through SRAM with NoBL™ Architecture

Last Updated: 
Apr 15, 2016
Version: 
*G

The CY7C1460SV33 is a 3.3 V, 1M × 36 synchronous pipelined burst SRAM with No Bus Latency™ (NoBL™) logic, respectively.