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CY7C1460SV25/CY7C1462SV25, 36-Mbit (1M × 36/2M × 18) Pipelined SRAM with NoBL™ Architecture | Cypress Semiconductor

CY7C1460SV25/CY7C1462SV25, 36-Mbit (1M × 36/2M × 18) Pipelined SRAM with NoBL™ Architecture

Last Updated: 
Apr 15, 2016
Version: 
*J

The CY7C1460SV25/CY7C1462SV25 are 2.5 V, 1M × 36/2M × 18 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL) logic, respectively. They are designed to support unlimited true back to back Read/Write operations with no wait states.