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CY7C1460AV25/CY7C1462AV25, 36-MBIT (1M X 36/2M X 18) PIPELINED SRAM WITH NOBL(TM) ARCHITECTURE | Cypress Semiconductor

CY7C1460AV25/CY7C1462AV25, 36-MBIT (1M X 36/2M X 18) PIPELINED SRAM WITH NOBL(TM) ARCHITECTURE

Last Updated: 
Jun 04, 2020
Version: 
*M

36-Mbit (1 M × 36/2 M × 18) Pipelined SRAM with NoBL™ Architecture

Features

  • Pin-compatible and functionally equivalent to ZBT™
  • Supports 250-MHz bus operations with zero wait states
    • Available speed grades are 250, 200 and 167 MHz
  • Internally self-timed output buffer control to eliminate the need to use asynchronous OE
  • Fully registered (inputs and outputs) for pipelined operation
  • Byte Write capability
  • 2.5 V core power supply
  • 2.5 V I/O power supply
  • Fast clock-to-output times
  • For more, see pdf
     

Functional Description

The CY7C1460AV25/CY7C1462AV25 are 2.5 V, 1 M × 36/2 M × 18 synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL?? logic, respectively. They are designed to support unlimited true back-to-back read/write operations with no wait states. The CY7C1460AV25/CY7C1462AV25 are equipped with the advanced NoBL logic required to enable consecutive read/write operations with data being transferred on every clock cycle.