CY7C1440AV25, CY7C1446AV25: 36-Mbit (1 M × 36/512 K × 72) Pipelined Sync SRAM | Cypress Semiconductor
CY7C1440AV25, CY7C1446AV25: 36-Mbit (1 M × 36/512 K × 72) Pipelined Sync SRAM
Last Updated:
Jan 08, 2016
Version:
*E
36-Mbit (1 M × 36/512 K × 72) Pipelined Sync SRAM
Features
- Supports bus operation up to 250 MHz
- Available speed grades are 250 and 167 MHz
- Registered inputs and outputs for pipelined operation
- 2.5 V core power supply
- 2.5 V I/O power supply
- Fast clock-to-output times
- Provide high-performance 3-1-1-1 access rate
- For more, see pdf.
Functional Description
The CY7C1440AV25/CY7C1446AV25 SRAM integrates 1 M × 36/512 K × 72 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK).
Related Files
| File Title | Language | Size | Last Updated |
|---|---|---|---|
 CY7C1440AV25, CY7C1446AV25 36-Mbit (1 M × 36/512 K × 72) Pipelined Sync SRAM Datasheet.pdf |
English | 842.48 KB | 01/08/2016 |