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CY7C1423KV18/CY7C1424KV18, 36-Mbit DDR II SIO SRAM Two-Word Burst Architecture | Cypress Semiconductor

CY7C1423KV18/CY7C1424KV18, 36-Mbit DDR II SIO SRAM Two-Word Burst Architecture

Last Updated: 
Jan 29, 2018

36-Mbit DDR II SIO SRAM Two-Word Burst Architecture


  • 36 Mbit density (2 M x 18, 1 M x 36)
  • 333 MHz clock for high bandwidth
  • Two-word burst for reducing address bus frequency
  • Double data rate (DDR) interfaces (data transferred at 666 MHz) at 333 MHz
  • Two input clocks (K and K) for precise DDR timing
    • SRAM uses rising edges only
  • Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches
  • Echo clocks (CQ and CQ) simplify data capture in high speed systems
  • Synchronous internally self timed writes
  • For more, see pdf 

Functional Description

The CY7C1423KV18, and CY7C1424KV18 are 1.8 V synchronous pipelined SRAMs, equipped with DDR II SIO (double data rate separate I/O) architecture. The DDR II SIO consists of two separate ports: the read port and the write port to access the memory array. The read port has data outputs to support read operations and the write port has data inputs to support write operations. The DDR II SIO has separate data inputs and data outputs to completely eliminate the need to turnaround” the data bus required with common I/O devices.

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