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CY7C1384D: 18-Mbit (512 K × 32) Pipelined SRAM | Cypress Semiconductor

CY7C1384D: 18-Mbit (512 K × 32) Pipelined SRAM

Last Updated: 
Jan 08, 2016
Version: 
*C

18-Mbit (512 K × 32) Pipelined SRAM

Features

  • Supports bus operation up to 166 MHz
  • Available speed grades are 166 MHz
  • Registered inputs and outputs for pipelined operation
  • 3.3 V core power supply
  • 2.5 V or 3.3 V I/O power supply
  • Fast clock-to-output times
  • Provides high performance 3-1-1-1 access rate
  • For more, see pdf

Functional Description

The CY7C1384D SRAM integrates 524,288 × 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive edge triggered clock input (CLK).

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Thank you for choosing our products. They come with all the know-how and passion that our engineers have put into it. As you probably already know, Cypress is now Infineon. This is a major step for our company, but also for the good of you. 

Reliability and business continuity are of utmost importance for us. Hence, we remain fully committed to honoring existing customer and distributor relationships. This includes offering the legacy Cypress product portfolio. We thank you very much for your trusting support.

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