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CY7C1371S 18-Mbit (512K × 36) Flow-Through SRAM with NoBL™ Architecture | Cypress Semiconductor

CY7C1371S 18-Mbit (512K × 36) Flow-Through SRAM with NoBL™ Architecture

Last Updated: 
Apr 15, 2016
Version: 
*F

The CY7C1371S is a 3.3 V, 512K × 36 Synchronous flow through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations with no wait state insertion.