You are here

CY7C1370DV25/CY7C1372DV25, 18-MBIT (512K X 36/1M X 18) PIPELINED SRAM WITH NOBL(TM) ARCHITECTURE | Cypress Semiconductor

CY7C1370DV25/CY7C1372DV25, 18-MBIT (512K X 36/1M X 18) PIPELINED SRAM WITH NOBL(TM) ARCHITECTURE

Last Updated: 
Jun 04, 2020
Version: 
*P

18-Mbit (512 K × 36/1 M × 18) Pipelined SRAM with NoBL™ Architecture

Features

  • Pin-compatible and functionally equivalent to ZBT™
  • Supports 200-MHz bus operations with zero wait states
    • Available speed grades are 200 and 167 MHz
  • Internally self-timed output buffer control to eliminate the need to use asynchronous OE
  • Fully registered (inputs and outputs) for pipelined operation
  • Byte write capability
  • Single 2.5 V core power supply (VDD)
  • 2.5 V I/O power supply (VDDQ)
  • Fast clock-to-output times
  • For more, see pdf
     

Functional Description

The CY7C1370DV25 and CY7C1372DV25 are 2.5 V, 512 K × 36 and 1-Mbit × 18 synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL™) logic, respectively. They are designed to support unlimited true back-to-back read/write operations with no wait states. The CY7C1370DV25 and CY7C1372DV25 are equipped with the advanced NoBL logic required to enable consecutive read/write operations with data being transferred on every clock cycle.