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CY7C1364CV33: 9-Mbit (256 K × 32) Pipelined Sync SRAM | Cypress Semiconductor

CY7C1364CV33: 9-Mbit (256 K × 32) Pipelined Sync SRAM

Last Updated: 
Aug 25, 2015
Version: 
*C

9-Mbit (256 K × 32) Pipelined Sync SRAM

 Features

  • Registered inputs and outputs for pipelined operation
  • 256 K × 32 common I/O architecture
  • 3.3 V core power supply (VDD)
  • 2.5 V/3.3 V I/O power supply (VDDQ)
  • Fast clock-to-output times
    • 3.5 ns (for 166-MHz device)
  • Provide high-performance 3-1-1-1 access rate
  • User-selectable burst counter supporting Intel® Pentium® interleaved or linear burst sequences
  • Separate processor and controller address strobes
  • Synchronous self-timed writes
  • Asynchronous output enable
  • Available in JEDEC-standard lead-free 100-pin TQFP package
  • TQFP Available with 3-Chip Enable
  • “ZZ” Sleep Mode Option

Functional Description

The CY7C1364CV33 SRAM integrates 256 K × 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth-expansion Chip Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BW[A:D], and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin.

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