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CY7C1354D: 9-Mbit (256 K × 36) Pipelined SRAM with NoBL™ Architecture | Cypress Semiconductor

CY7C1354D: 9-Mbit (256 K × 36) Pipelined SRAM with NoBL™ Architecture

Last Updated: 
May 30, 2020
Version: 
*C

9-Mbit (256 K × 36) Pipelined SRAM with NoBL™ Architecture

Features

  • Pin-compatible and functionally equivalent to ZBT
  • Supports 200 MHz bus operations with zero wait states
    • Available speed grade is 200 MHz
  • Internally self-timed output buffer control to eliminate the need to use asynchronous OE
  • Fully registered (inputs and outputs) for pipelined operation
  • Byte write capability
  • Single 3.3 V power supply (VDD)
  • 3.3 V or 2.5 V I/O power supply (VDDQ)
  • Fast clock-to-output times
    • 3.2 ns (for 200 MHz device)
  • For more, see pdf

Functional Description

The CY7C1354D are 3.3 V, 256 K × 36 synchronous pipelined burst SRAM with No Bus Latency™ (NoBL™) logic, respectively. They are designed to support unlimited true back-to-back read/write operations with no wait states. The CY7C1354D are equipped with the advanced (NoBL) logic required to enable consecutive read/write operations with data being transferred on every clock cycle.

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