CY7C1352G: 4-Mbit (256 K × 18) Pipelined SRAM with NoBL™ Architecture | Cypress Semiconductor
CY7C1352G: 4-Mbit (256 K × 18) Pipelined SRAM with NoBL™ Architecture
Last Updated:
Nov 21, 2016
Version:
*O
4-Mbit (256 K × 18) Pipelined SRAM with NoBL™ Architecture
Features
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Pin compatible and functionally equivalent to ZBT™ devices
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Internally self-timed output buffer control to eliminate the need to use OE
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Byte write capability
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256 K × 18 common I/O architecture
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3.3 V core power supply (VDD)
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2.5 V/3.3 V I/O power supply (VDDQ)
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Fast clock-to-output times
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4.0 ns (for 133-MHz device)
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Clock enable (CEN) pin to suspend operation
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For more, see pdf
Functional Description
The CY7C1352G is a 3.3 V, 256 K × 18 synchronous-pipelined burst SRAM designed specifically to support unlimited true back-to-back read/write operations without the insertion of wait states. The CY7C1352G is equipped with the advanced No Bus Latency™ (NoBL™) logic required to enable consecutive read/write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of the SRAM, especially in systems that require frequent write/read transitions.
Related Files
| File Title | Language | Size | Last Updated |
|---|---|---|---|
 CY7C1352G 4-Mbit (256 K × 18) Pipelined SRAM with NoBL Architecture Datasheet.pdf |
English | 1.93 MB | 11/21/2016 |