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CY7B9910, Low Skew Clock Buffer | Cypress Semiconductor

CY7B9910, Low Skew Clock Buffer

Last Updated: 
Nov 27, 2017

Low Skew Clock Buffer


  • All outputs skew < 100 ps typical (250 max)
  • 15 to 80 MHz output operation
  • Zero input to output delay
  • 50% duty cycle outputs
  • Outputs drive 50 Ω terminated lines
  • Low operating current
  • 24-pin small-outline integrated circuit (SOIC) package
  • Jitter: < 200 ps peak-to-peak, < 25 ps RMS

Functional Description

The CY7B9910 and CY7B9920 low skew clock buffers offer low skew system clock distribution. These multiple output clock drivers optimize the timing of high performance computer systems. Each of the eight individual drivers can drive terminated transmission lines with impedances as low as 50Ω. They deliver minimal and specified output skews and full swing logic levels (CY7B9910 TTL or CY7B9920 CMOS).