CY2DP818: 1:8 Clock Fanout Buffer | Cypress Semiconductor
CY2DP818: 1:8 Clock Fanout Buffer
1:8 Clock Fanout Buffer
Low-voltage operation VDD = 3.3V
Operation to 350 MHz
Single input configurable for LVDS, LVPECL, or LVTTL
8 pair of LVPECL outputs
Drives a 50 ohm load
Low input capacitance
Low output skew
Low propagation delay (tpd = 4 ns, typical)
Commercial and Industrial temperature ranges
38-Pin TSSOP Package
For more, see pdf
The Cypress CY2DP818 fanout buffer features a single LVDS or a single ended LVTTL compatible input and eight LVPECL output pairs.
Designed for data-communications clock management applications, the large fanout from a single input reduces loading on the input clock.
The CY2DP818 is ideal for both level translations from single ended to LVPECL and/or for the distribution of LVPECL based clock signals.
The Cypress CY2DP818 has configurable input functions. The input is user configurable via the InConfig pin for single ended or differential input.
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