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CY23S09, CY23S05: Low Cost 3.3 V Spread Aware Zero Delay Buffer | Cypress Semiconductor

CY23S09, CY23S05: Low Cost 3.3 V Spread Aware Zero Delay Buffer

Last Updated: 
Jun 14, 2017
Version: 
*I

Low Cost 3.3V Spread Aware Zero Delay Buffer

Features

  • 10 MHz to 100 and 133 MHz Operating Range, compatible with CPU and PCI bus frequencies
  • Zero Input-output Propagation Delay
  • Multiple Low Skew Outputs
    • Output-output skew less than 250 ps
    • Device-device skew less than 700 ps
    • One input drives five outputs (CY23S05)
    • One input drives nine outputs, grouped as 4 4 1 (CY23S09)
  • Less than 200 ps Cycle-to-cycle jitter is compatible with Pentium based systems
  • Test mode to bypass PLL
  • Available in space saving 16-pin, 150-mil SOIC, 4.4 mm TSSOP, and 150-mil SSOP (CY23S09) or 8-pin, 150-mil SOIC package (CY23S05)
  • 3.3V operation, advanced 0.65μ CMOS Technology
  • Spread Aware
     

Functional Description

The CY23S09 is a low cost 3.3 V zero delay buffer designed to distribute high speed clocks and is available in a 16-pin SOIC package. The CY23S05 is an 8-pin version of the CY23S09. It accepts one reference input, and drives out five low skew clocks. The -1H versions of each device operate at up to 100 and 133 MHz frequencies and have higher drive than the -1 devices.

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