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CY23FP12: 200 MHz Field Programmable Zero Delay Buffer | Cypress Semiconductor

CY23FP12: 200 MHz Field Programmable Zero Delay Buffer

Last Updated: 
Mar 21, 2017

200 MHz Field Programmable Zero Delay Buffer


  • Fully Field-Programmable
    • Input and output dividers
    • Inverting/noninverting outputs
    • Phase-locked loop (PLL) or fanout buffer configu­ration
  • 10 MHz to 200 MHz Operating Range
  • Split 2.5V or 3.3V Outputs
  • Two LVCMOS Reference Inputs
  • Twelve Low Skew Outputs
    • 35 ps typical output-to-output skew (same frequency)
  • For more, see pdf

Functional Description

The CY23FP12 is a high performance fully field-programmable 200 MHz zero delay buffer designed for high speed clock distribution. The integrated PLL is designed for low jitter and optimized for noise rejection. These parameters are critical for reference clock distribution in systems using high performance ASICs and microprocessors.

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