CY23FP12: 200 MHz Field Programmable Zero Delay Buffer | Cypress Semiconductor
CY23FP12: 200 MHz Field Programmable Zero Delay Buffer
Last Updated:
Mar 21, 2017
Version:
*K
200 MHz Field Programmable Zero Delay Buffer
Features
- Fully Field-Programmable
- Input and output dividers
- Inverting/noninverting outputs
- Phase-locked loop (PLL) or fanout buffer configuration
- 10 MHz to 200 MHz Operating Range
- Split 2.5V or 3.3V Outputs
- Two LVCMOS Reference Inputs
- Twelve Low Skew Outputs
- 35 ps typical output-to-output skew (same frequency)
- For more, see pdf
Functional Description
The CY23FP12 is a high performance fully field-programmable 200 MHz zero delay buffer designed for high speed clock distribution. The integrated PLL is designed for low jitter and optimized for noise rejection. These parameters are critical for reference clock distribution in systems using high performance ASICs and microprocessors.
Dear valued customer,
Thank you for choosing our products. They come with all the know-how and passion that our engineers have put into it. As you probably already know, Cypress is now Infineon. This is a major step for our company, but also for the good of you.
Reliability and business continuity are of utmost importance for us. Hence, we remain fully committed to honoring existing customer and distributor relationships. This includes offering the legacy Cypress product portfolio. We thank you very much for your trusting support.
For the full version of this message, please download the PDF version.
Related Files
| File Title | Language | Size | Last Updated |
|---|---|---|---|
 CY23FP12: 200 MHz Field Programmable Zero Delay Buffer Datasheet.pdf |
English | 450.4 KB | 03/21/2017 |