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Last Updated: 
May 28, 2020


  • 16-Mbit nonvolatile static random access memory (nvSRAM)
    • Performance up to 33 MT/s per I/O
    • Maximum data throughput using ×16 bus – 528 Mbps
    • Industry-standard asynchronous NAND Flash interface with reduced instruction set
    • Shared address, data, and command bus
      • Address and command bus is 8 bits
      • Command is sent in one or two command cycles
      • Address is sent in five address cycles
      • Data bus width is ×8 or ×16 bits
  • Modes of operation:
    • Asynchronous NAND Interface I/O with 30-ns access time
    • Status Register with a software method for detecting the following:
      • Nonvolatile STORE completion
      • Pass/Fail condition of previous command
      • Write protect status
  • Hands-off automatic STORE on power-down with only a small capacitor
  • STORE to QuantumTrap nonvolatile elements is initiated by a software command, a dedicated hardware pin, or AutoStore on power-down
  • RECALL to SRAM initiated by software or power-up
  • High reliability
    • Infinite read, write, and RECALL cycles
    • 1 million STORE cycles to QuantumTrap
  • Data retention: 20 years at 85 °C
  • Operating voltage
    • Core VCC = 2.7 V to 3.6 V; I/O VCCQ = 1.70 V to 1.95 V
  • 165-ball fine-pitch ball grid array (FBGA) package
  • Industrial temperature: –40 °C to +85 °C
  • Restriction of hazardous substances (RoHS) compliant


Cypress nvSRAM combines high-performance SRAM cells with nonvolatile elements in a monolithic integrated circuit. The embedded nonvolatile elements incorporate the Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) technology, producing the world's most reliable nonvolatile memory. The SRAM can be read and written an infinite number of times. The nonvolatile data resides in the nonvolatile elements and does not change when data is written to the SRAM.

The CY14V116F7/CY14V116G7 nvSRAM provides access through a standard asynchronous NAND interface and supports the ×8 and ×16 interface options. In the case of ×16 interface, data bytes are transmitted over the DQ[15:0] lines and has double the throughput compared to the DQ[7:0] bus. The CY14V116F7/ CY14V116G7 uses a highly multiplexed DQ bus to transfer data, addresses, and instructions. All addresses and commands are always transmitted over the data bus DQ[7:0]. Therefore, in the case of the ×16 bus interface, the upper eight data bits DQ[15:8] become don’t care bits during the address and command cycles. The CY14V116F7/CY14V116G7 uses five control pins (CLE, ALE, CE, RE, and WE) to transfer command, address, and data during read and write operations. Additional I/O pins, such as write protect (WP), ready/busy (R/B), and HSB STORE, are used to support features in the device.

The asynchronous NAND interface nvSRAM is aligned to a majority of the ONFI 1.0 specifications and supports data access speed up to 33 MHz.

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