CY14B512Q1, CY14B512Q2, CY14B512Q3: 512-Kbit (64 K × 8) Serial (SPI) nvSRAM | Cypress Semiconductor
CY14B512Q1, CY14B512Q2, CY14B512Q3: 512-Kbit (64 K × 8) Serial (SPI) nvSRAM
- 512-Kbit nonvolatile static random access memory (nvSRAM)
- Internally organized as 64 K × 8
- STORE to QuantumTrap nonvolatile elements initiated automatically on power-down (AutoStore) or by user using HSB pin (hardware STORE) or SPI instruction (Software STORE)
- RECALL to SRAM initiated on power-up (power-Up RECALL) or by SPI instruction (software RECALL)
- Automatic STORE on power-down with a small capacitor (except for CY14B512Q1)
- High reliability
- Infinite read, write, and RECALL cycles
- 1 million STORE cycles to QuantumTrap
- Data retention: 20 years
- High speed serial peripheral interface (SPI)
- 40 MHz clock rate
- Supports SPI mode 0 (0,0) and mode 3 (1,1)
- Write protection
- Hardware protection using Write Protect (WP) pin
- Software protection using Write Disable instruction
- Software block protection for 1/4,1/2, or entire array
- Low power consumption
- Single 3 V +20%, –10% operation
- Average active current of 10 mA at 40 MHz operation
- Industry standard configurations
- Industrial temperature
- CY14B512Q1 has identical pin configuration to industry standard 8-pin NV memory
- 8-pin dual flat no-lead (DFN) package and 16-pin small outline integrated circuit (SOIC) package
- Restriction of hazardous substances (RoHS) compliant
The Cypress CY14B512Q1/CY14B512Q2/CY14B512Q3 combines a 512-Kbit nvSRAM with a nonvolatile element in each memory cell with serial SPI interface. The memory is organized as 64 K words of 8 bits each. The embedded nonvolatile elements incorporate the QuantumTrap technology, creating the world’s most reliable nonvolatile memory. The SRAM provides infinite read and write cycles, while the QuantumTrap cell provides highly reliable nonvolatile storage of data. Data transfers from SRAM to the nonvolatile elements (STORE operation) takes place automatically at power-down (except for CY14B512Q1). On power-up, data is restored to the SRAM from the nonvolatile memory (RECALL operation). The STORE and RECALL operations can also be initiated by the user through SPI instruction.
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