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Voltage DAC (12-bit) (VDAC12) | Cypress Semiconductor

Voltage DAC (12-bit) (VDAC12)

Last Updated: 
Jun 24, 2020
Features Symbol Diagram
  • 12-bit continuous-time DAC
  • Selectable voltage references:
    • Analog supply voltage (VDDA)
    • Buffered internal analog reference
    • Buffered external reference
  • Selectable output paths:
    • Direct DAC output to a pin or to an internal Component
    • Buffered DAC output to a pin or to an internal Component
  • Selectable input modes:
    • 12-bit unsigned mode
    • 12-bit two's-complement mode
  • Optional sample and hold circuit connection for low power Deep Sleep operation
  • 500 ksps maximum programmable update rate
  • Interrupt and DMA trigger on DAC buffer empty
  • Can be enabled (but not updated) in Deep Sleep power mode

VDAC Diagram


General Description

The VDAC12 is a 12-bit DAC based on a resistor ladder DAC. The core is closely integrated with the Continuous Time Block (CTB), which provides easy buffering of the DAC output voltage through one of its opamps. The CTB can additionally provide a buffered input reference voltage and a sample/hold feature for reduced power while maintaining the DAC output. See the Technical Reference Manual (TRM) for details on the CTB. The DAC reference can come from VDDA or from any buffered signal though the CTB opamp. This can be an external signal through a GPIO or from the analog reference (AREF). The control interface provides an option to control the DAC output through CPU and DMA. This includes a double buffered DAC voltage control register, clock input for programmable update rate, interrupt on DAC buffer empty to CPU, and trigger to DMA.