Interrupt

Features

• Defines hardware-triggered interrupts
• Provides a software method to pend interrupt

General Description

The Interrupt component defines hardware triggered interrupts. It is an integral part of the Interrupt Design-Wide Resource system (see PSoC Creator Help, Design-Wide Resources section).

There are three types of system interrupt waveforms that can be processed by the interrupt controller:

• Level – IRQ source is sticky and remains active until firmware clears the source of the request with an action (for example clear on read). Most fixed-function peripherals have level-sensitive interrupts, including the UDB FIFOs and status registers.
• Pulse – Ideally, a pulse IRQ is a single bus clock, which logs a pending action and ensures that the ISR action is only executed once. No firmware action to the peripheral is required.
• Edge – An arbitrary synchronous waveform is the input to an edge-detect circuit and the positive edge of that waveform becomes a synchronous one-cycle pulse (Pulse mode).