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I2C (SCB_I2C_PDL) | Cypress Semiconductor

I2C (SCB_I2C_PDL)

Last Updated: 
Mar 26, 2018
Version: 
2.0
Features Symbol Diagram
  • Industry-Standard NXP I2C bus interface
  • Supports slave, master and master-slave operation
  • Supports data rates of 100/400/1000 kbps
  • Hardware Address Match, multiple addresses
  • Wake from Deep Sleep on Address Match
  • Peripheral Driver Library (PDL) Component (PDL Application Programming Interface (API) only)
 

SCB I2C Diagram

 

General Description

The SCB_I2C_PDL Component supports I2C slave, master, and master-slave operation configurations. The I2C bus is an industry-standard, two-wire hardware interface developed by Philips. The master initiates all communication on the I2C bus and supplies the clock for all slave devices.

The SCB_I2C_PDL Component supports standard clock speeds up to 1000 kbps. It is compatible with I2C Standard-mode, Fast-mode, and Fast-mode Plus devices as defined in the NXP I2C-bus specification. The SCB_I2C_PDL Component is compatible with other third-party slave and master devices.

The SCB_I2C_PDL Component is a graphical configuration entity built on top of the cy_scb driver available in the PDL. It allows schematic-based connections and hardware configuration as defined by the Component Configure dialog.