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EZI2C (SCB_EZI2C_PDL) | Cypress Semiconductor


Last Updated: 
Jun 25, 2020
Features Symbol Diagram
  • Industry-Standard I2C bus interface
  • Supports data rates of 100/400/1000 kbps
  • Emulates common I2C EEPROM Interface
  • Acts like dual port memory between the external master and your code
  • Hardware Address Match
  • Supports two hardware addresses with separate buffers
  • Wake from Deep Sleep on address match
  • Simple to setup and use. Once setup no need to call EZI2C API in run time
  • Peripheral Driver Library (PDL) Component (PDL Application Programming Interface (API) only)

SCB EZI2C Diagram


General Description

The SCB_EZI2C_PDL Component is a unique implementation of an I2C slave in that all communication between the master and slave is handled in the Interrupt Service Routine (ISR). It requires no interaction with the main program flow. The interface appears as shared memory between the master and slave.

The SCB_EZI2C_PDL Component is a graphical configuration entity built on top of the cy_scb driver available in the PDL. It allows schematic-based connections and hardware configuration as defined by the Component Configure dialog.