Direct Memory Access (DMA) | Cypress Semiconductor

Direct Memory Access (DMA)

Last Updated:

Mar 19, 2018

Version:

1.70

Features

24 channels
Eight priority levels
128 Transaction Descriptors (TDs)
8-, 16-, and 32-bit data transfers
Configurable source and destination addresses
Support for endian compatibility
Can generate an interrupt when data transfer is complete
DMA Wizard to assist with application development

Symbol Diagram
DMA Segmatic

General Description

The DMA component allows data transfers to and from memory, components, and registers. The controller supports 8-, 16-, and 32-bit wide data transfers, and can be configured to transfer data between a source and destination that have different endianess. TDs can be chained together for complex operations.

Translated documents are for reference only. We recommend that you refer to the English-language version of a document if you are engaged in development of a design.

Related Files

File Title	Language	Size	Last Updated
Component - Direct Memory Access V1.70 Datasheet.pdf	English	368.96 KB	09/21/2016
Component - Direct Memory Access V1.60 Datasheet.pdf	English	483.27 KB	09/21/2016
Component - Direct Memory Access V1.50 Datasheet.pdf	English	539.94 KB	09/21/2016
Component - Direct Memory Access V1.70 Datasheet (Chinese).pdf	Chinese	801.61 KB	09/21/2016
Component - Direct Memory Access V1.50 Datasheet (Chinese).pdf	Chinese	406.84 KB	08/10/2015
Component - Direct Memory Access V1.50 Datasheet (Japanese).pdf	Japanese	522.36 KB	08/10/2015