Digital Filter Block (DFB) Assembler

Features

Symbol Diagram

Provides an editor to enter the assembler instructions to configure the DFB block and an assembler that converts the assembly instructions to instruction words. Supports simulation of the assembly instructions. Supports a code optimization option that provides a mechanism to incorporate up to 128 very large instruction words inside the DFB Code RAM. Provides hardware signals such as DMA requests, DSI inputs and outputs, and interrupt lines. Supports semaphores to interact with the system software and the option to tie the semaphores to hardware signals.

General Description

The digital filter block (DFB) in PSoC 3 and PSoC 5LP can be used as mini DSP processor and allows you to configure the DFB using assembly instructions. The component assembles the instructions entered in the editor and generates the corresponding hex code words, which can be loaded into the DFB. It also includes a simulator, which helps the user to simulate and debug the assembly instructions.

The DFB consists of a programmable 24*24 multiplier/accumulator (MAC), an arithmetic logic unit (ALU), shifter, and various program and data memory to store instructions and data. The DFB runs on the bus clock, and can interface with both CPU and DMA. It can be used to offload the CPU and can speed up arithmetic calculations that involve intensive multiply accumulate operations. Typical operations you can use the DFB component to implement include: vector operations, matrix operations, filtering operations, and signal processing.