Clock (SysClk_PDL) | Cypress Semiconductor
Clock (SysClk_PDL)
Last Updated:
Jun 24, 2020
Version:
1.0
Features | Symbol Diagram |
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General Description The SysClk_PDL Component provides an interface to the programmable peripheral clock dividers. It allows you to configure the dividers by specifying a frequency with tolerance, or by specifying a divider. |