PSoC® 3 and PSoC® 5LP CapSense® Design Guide | Cypress Semiconductor
PSoC® 3 and PSoC® 5LP CapSense® Design Guide
May 28, 2020
This document provides design guidance for building CapSense applications with the PSoC 3 and PSoC 5LP family of devices.
Translated documents are for reference only. We recommend that you refer to the English-language version of a document if you are engaged in development of a design.