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AN89371 - Power Saving With Cypress’s 65-nm Asynchronous PowerSnooze™ SRAM | Cypress Semiconductor

AN89371 - Power Saving With Cypress’s 65-nm Asynchronous PowerSnooze™ SRAM

Last Updated: 
Aug 26, 2015
Version: 
*A

This application note explains the PowerSnoozeTM feature of Cypress’ 65-nm Asynchronous Fast SRAM devices (CY7S10xxG family). PowerSnooze allows the SRAM to enter into a low-power mode during long chip disable periods. A user-controlled pin (DS) allows seamless transition between high-speed mode and low-power mode. This application note also describes the critical timing parameters for the mode transitions as well as a sample SRAM interface configuration to use the PowerSnooze feature in application systems.

Introduction

With the advent of mobile technology and portable battery-backed devices, power consumption has become one of the key factors in system design. System designers face the dilemma of selecting between faster operating speeds and lower power consumption for the microcontrollers/ASICs, peripherals, and memory devices in their systems.

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