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AN87216 - Designing a GPIF II Master Interface | Cypress Semiconductor

AN87216 - Designing a GPIF II Master Interface

Last Updated: 
May 09, 2019


Cypress’s FX3 is a USB 3.0 peripheral controller, which provides highly integrated and flexible features to enable developers to add USB 3.0 functionality to any system.

FX3 has a configurable, parallel, general programmable interface, called GPIF II, which is Cypress’s General Programmable Interface, generation II. GPIF II can connect to an external processor, ASIC, or FPGA. GPIF II provides glueless connectivity to widely used interfaces, such as asynchronous SRAMs as well as asynchronous and synchronous address data multiplexed interfaces.

AN87216 shows how to design an EZ-USB® FX3™ master interface to communicate with an external synchronous Slave FIFO. The design uses the FX3 GPIF™ II Designer tool to develop the interface using a graphical state machine entry. To test this design, we connected two FX3 development kits back to back over the GPIF II interface, one acting as the master (the subject of this note) and the other as a test slave. Firmware source code and GPIF II state machines for both master and slave FX3 kits are attached to this application note.

Please refer to the SuperSpeed Code Examples for more examples.

Translated documents are for reference only. We recommend that you refer to the English-language version of a document if you are engaged in development of a design.