You are here

AN64574 - Designing with Serial Peripheral Interface (SPI) nvSRAM | Cypress Semiconductor

AN64574 - Designing with Serial Peripheral Interface (SPI) nvSRAM

Last Updated: 
May 28, 2020

Cypress’s serial peripheral interface (SPI) nvSRAM is a high-performance nonvolatile serial memory that offers zero cycle delay write operation and infinite SRAM write endurance. The SPI nvSRAM is a slave SPI device and requires an SPI master controller to access nvSRAM in a system. This application note provides a few key design considerations and firmware tips to guide the users designing with SPI nvSRAM. An associated project for PSoC 1 and a library component for PSoC 3 and PSoC 4 are also provided as an example project, which demonstrates SPI nvSRAM access by a standard SPI master controller.

SOC connection to SPI nvSRAM Diagram

Translated documents are for reference only. We recommend that you refer to the English-language version of a document if you are engaged in development of a design.