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AN61345 - Designing with EZ-USB® FX2LP™ Slave FIFO Interface | Cypress Semiconductor

AN61345 - Designing with EZ-USB® FX2LP™ Slave FIFO Interface

Last Updated: 
Mar 03, 2021
Version: 
*L
AN61345 provides a sample project to interface an FX2LP™ with FPGA using Slave FIFO interface. The interface, described in the sample implementation, adds High-Speed USB connectivity to applications such as data acquisition, industrial control and monitoring, and image processing. The project provided with this application note is implemented and tested with Xilinx® Spartan® 6 FPGA.

Dear valued customer,

Thank you for choosing our products. They come with all the know-how and passion that our engineers have put into it. As you probably already know, Cypress is now Infineon. This is a major step for our company, but also for the good of you. 

Reliability and business continuity are of utmost importance for us. Hence, we remain fully committed to honoring existing customer and distributor relationships. This includes offering the legacy Cypress product portfolio. We thank you very much for your trusting support.

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Translated documents are for reference only. We recommend that you refer to the English-language version of a document if you are engaged in development of a design.